Bus performance evaluation method for algorithm description

ABSTRACT

The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation platform structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general purpose high-level language such as the C language and C++ language. In the simulation platform structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting between the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is to be finally produced. That is, the result of the bus performance evaluation process is fed back to the simulation platform structuring process such that isolation of the hardware and software is optimized in response to the bus traffic for the processing rate of the bus. This brings exclusion of feedback loops derived from the cooperative verification after the actual coding, so it is possible to considerably reduce overall turnaround time of design.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention is provided for verification of algorithms in order to facilitate architecture designs at high-level stages of design. Specifically, this invention relates to bus performance evaluation methods for algorithm descriptions in which evaluation is performed on performances of buses interconnecting between the hardware and software by use of sources described by general purpose high-level languages such as the C language and C++ language.

[0003] 2. Description of the Related Art

[0004] Due to the recent developments of the semiconductor technologies, there are tendencies for the physical hardware system to be frequently actualized by a single LSI chip rather than by plural LSI chips arranged on boards. For this reason, signals of the LSI chips that are conventionally interconnected with external terminals are translated to internal signals and are incorporated within the LSI chips in these days. To verify the conventional systems using the boards, it is necessary to produce LSI devices specifically for use in evaluation that is performed as if all internal signals are interconnected with external terminals. However, it is troublesome for manufacturers to perform verification on the systems by using the specifically designed LSI devices. Actually, the recent developments raise a difficulty in which verification is difficult to perform using the foregoing boards.

[0005]FIG. 11 shows a flow of steps showing the conventional procedures for the design and development of LSI (hereinafter, simply referred to as LSI design and development) in manufacture of logic circuits, systems and devices. Prior to the actual manufacturing, simulation platforms (or algorithms) are normally structured without consideration of distinctions between the hardware and software (see step B1). In step B2, verification is made as to whether the algorithms are correctly made or not. Next, isolation of the hardware and software is performed on the structured simulation platforms, which are divided into hardware elements and software elements respectively. The isolation of the hardware and software is made by experiments.

[0006] In the hardware design (or H/W design), sources having equivalent functions of the algorithms are generally described by HDL (which stands for ‘Hardware Description Language’), then, composition of circuitry is carried out (see step B3). In step B4, verification is made as to whether the sources operate normally or not. In the software design (or S/W design), sources having equivalent functions of the algorithms are generally described by the programming language having a CPU dependency (see step B5). In step B6, verification is made as to whether the sources operate normally or not. Lastly, cooperative verification is performed on combinations of the hardware and software (see step B7).

[0007] Prior to the actual manufacturing of LSI, the procedures for the LSI design and development should meet some essential conditions raising requirements of the system simulation and bus performance evaluation as well as the architecture design in which isolation of the hardware and software is performed by simulation. Conventionally, the system simulation is performed by the cooperative verification on the unification of the hardware and software.

[0008] Due to rapid increases in scales of integrated circuits being manufactured in these days, it becomes necessary to provide considerably large numbers of codes for use in description of the circuits to be created. This causes considerable reduction in simulation speed of the cooperative verification on descriptions using the HDL or other programming languages each having a CPU dependency. In practice, it becomes very difficult to perform the architecture design using the cooperative verification.

[0009] In the architecture design using the cooperative verification, there may occur necessities of modifications on buses interconnecting between the hardware and software due to results of evaluation of performances of the buses. In that case, it is necessary to modify the HDL or other programming languages each having a CPU dependency (see steps B8, B9 in FIG. 11).

[0010] Due to increasing numbers of codes for use in description of the circuits to be created, circuit descriptions must become more and more complicated, which in turn cause complicity in modifications of the circuit descriptions. That is, it takes much time and cost to perform operations regarding feedback loops being derived from results of the cooperative verification. Recently, there are tendencies in which periods for developments of LSI are considerably reduced while the circuit scales are increased more and more. To cope with such tendencies, the procedures of the LSI design and development should meet some essential conditions in which evaluation of performances of the buses interconnecting between the hardware and software and the architecture design are performed at high-level stages of design respectively.

SUMMARY OF THE INVENTION

[0011] It is an object of the invention to provide a bus performance evaluation method for algorithm description by which it is possible to considerably reduce turnaround times in design of LSI by excluding unwanted operations regarding feedback loops derived from cooperative verification in the hardware design and software design. Basically, this invention provides improvements in procedures for the design and development of LSI. That is, after isolation of the hardware and software being effected with respect to sources described by the general purpose high-level language in algorithm design, an evaluation function is created to count traffic of the bus interconnecting between the hardware and software. The sources are modified such that the evaluation function is performed every time data (e.g., a variable) is loaded onto the bus. Then, evaluation is performed on the performance of the bus having a processing rate. Based on the bus traffic that is finally produced with respect to the processing rate, isolation of the hardware and software is optimally performed at the prescribed stage of the architecture design. Thus, it is possible to exclude the feedback loops regarding the isolation between the hardware and software from the cooperative verification after the actual coding. As a result, it is possible to considerably reduce the turnaround time in the design of LSI.

[0012] More specifically, the LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation platform structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general purpose high-level language such as the C language and C++ language. In the simulation platform structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting between the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is finally produced. That is, result of the bus performance evaluation process is fed back to the simulation platform structuring process such that isolation of the hardware and software is optimized in response to the bus traffic for the processing rate of the bus. This results in exclusion of feedback loops derived from the cooperative verification after the actual coding, so it is possible to considerably reduce overall turnaround time of design.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] These and other objects, aspects and embodiments of the present invention will be described in more detail with reference to the following drawing figures, of which:

[0014]FIG. 1 is a flowchart showing procedures for design and development of LSI in accordance with the invention;

[0015]FIG. 2 shows a list form representing a bus performance evaluation method in accordance with a first embodiment of the invention;

[0016]FIG. 3 shows a list form representing a simulation platform that is restructured in accordance with the first embodiment shown in FIG. 2;

[0017]FIG. 4 is a flowchart showing procedures of works that are effected by the first embodiment shown in FIG. 2;

[0018]FIG. 5 shows a list form representing a bus performance evaluation method in accordance with a second embodiment of the invention;

[0019]FIG. 6 shows a list form representing a bus performance evaluation method in accordance with a third embodiment of the invention;

[0020]FIG. 7 shows a list form representing a bus performance evaluation method in accordance with a fourth embodiment of the invention;

[0021]FIG. 8 shows a list form representing a bus performance evaluation method in accordance with a fifth embodiment of the invention;

[0022]FIG. 9 shows a list form representing a bus performance evaluation method in accordance with a sixth embodiment of the invention;

[0023]FIG. 10 shows a list form representing a simulation platform that is structured using sources described by the C++ language; and

[0024]FIG. 11 is a flowchart showing procedures for the conventional design and development of LSI.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] This invention will be described in further detail by way of examples with reference to the accompanying drawings.

[0026]FIG. 1 shows a flow of procedures for design and development of LSI in accordance with the invention. As compared with the conventional flow of procedures for the LSI design and development that is described in conjunction with FIG. 11, the present flow shown in FIG. 1 is facilitated in manufacture to enable the architecture design at the high-level stage of design and is characterized by adding a simulation platform structuring process and a bus performance evaluation process (see step A15). Details of these processes will be described below.

[0027] In step A1, algorithms are designed for logic circuits, devices and systems to be manufactured. In step A2, verification is made as to whether the algorithms are made correctly or not.

[0028] Next, a simulation platform is structured to perform architecture design by using sources, which are used in the aforementioned algorithm design. Namely, in the simulation platform structuring process, the flow proceeds to step A3 to effect isolation of the hardware and software. In step A4, an evaluation function is created. Herein, it is satisfactory that the evaluation function has an operation of counting a certain value.

[0029] In step A5, variables loaded onto the bus interconnecting between the hardware and software are being selected. Then, the flow proceeds to step A6 in which sources that are used in the algorithm design are modified by executing the created evaluation function when data are written to the variables loaded onto the bus, in other words, when data transfer is effected on the bus that is a subject of evaluation (hereinafter, simply referred to as the ‘evaluated’ bus). In response to modifications of the sources, the simulation platform for use in the architecture design is structured again.

[0030] Next, evaluation is performed on the performance of the bus, which is a subject of evaluation, by using the structured simulation platform. That is, in the performance evaluation process, the flow proceeds to step A7 in which verification is performed using the structured simulation platform. In step A8, bus traffic is calculated by the prescribed method, which depends on the created evaluation function. Herein, a processing rate requested by a main function is already known. Hence, the bus traffic is calculated with respect to the processing rate of the evaluated bus in step A9.

[0031] Using the bus traffic that is calculated in response to the processing rate, it is possible to check validity with respect to isolation of the hardware and software and a bus configuration. If the validity check causes a change of the bus, the sources that are described by the general purpose high-level language such as the C language and C++ language are modified, then, the simulation platform is structured again and the performance evaluation is performed again. That is, the present procedures provide a feedback loop (see step A16) for feeding back the result of the performance evaluation of the bus. Due to provision of such a feedback loop, it is possible to actualize the architecture design at the high-level stage of design.

[0032] After completion of the architecture design in step A15, the flow proceeds to the hardware design (HIW design) and the software design (S/W design) respectively. In the hardware design, sources having equivalent functions of the algorithm(s) are generally described by the HDL (i.e., Hardware Description Language), then, composition of circuitry is performed in step A10. In step A11, verification is made as to whether the sources operate normally or not. In the software design, sources having equivalent functions of the algorithm(s) are generally described by the programming language having a CPU dependency in step A12. In step A13, verification is made as to whether the sources operate normally or not.

[0033] In step A14, cooperative verification is performed on unification of the hardware and software. In the present flow of procedures for the design and development of LSI, the architecture design is already completed at the high-level stage of design. This places the cooperative verification as one type of simulation for making operational confirmation only, in which no design is newly made. Namely, this eliminates the necessity to provide feedback loops being derived from the cooperative verification.

[0034]FIG. 2 shows a list form representing a bus performance evaluation method in accordance with the first embodiment of the invention. With reference to FIG. 2, there are provided three variables, namely ‘a’, ‘b’ and ‘c’ being loaded onto the evaluated bus, wherein all of the variables are subjected to global definition. In addition, there are provided an evaluation function ‘BUS0( )’ and a local variable ‘bus0’. Herein, the evaluation function increments a static variable i to provide a return value. The local variable bus0 stores the return value from the evaluation function BUS0( ). Namely, it represents a number of times in effecting data transfer on the evaluated bus. The same number of bits are set to binary representations of the three variables a, b, c being loaded onto the evaluated bus. Herein, the number of bits of each variable is smaller than the number of lines (or bits) of the evaluated bus.

[0035] The first embodiment shown in FIG. 2 is designed to certainly execute the evaluation function BUS0( ) when data are written to the variables a, b, c loaded onto the evaluated bus. So, the evaluation function BUS0( ) is embedded subsequent to (or just after) the variables to which data are written respectively. Every time the evaluation function BUS0( ) is executed, the static variable i is incremented to provide a return value. The return value from the evaluation function BUS0( ) represents the number of times in writing data to the variables loaded onto the evaluated bus.

[0036] In addition, the number of times in writing the data to the variables loaded onto the evaluated bus represents a number of times in effecting data transfer on the evaluated bus, namely bus traffic. Because the processing rate requested by the main function is already known, it is possible to calculate the bus traffic for the processing rate and effect performance evaluation in accordance with the following equation (1).

(Bus traffic for the processing rate)=(number of times in effecting data transfer)/(processing rate)  (1)

[0037] To change the bus interconnecting between the hardware and software in response to the bus traffic being calculated for the processing rate, the sources used in the algorithm design are modified so that the simulation platform is to be structured again.

[0038]FIG. 3 shows an example of the ‘restructured’ simulation platform. With reference to the restructured simulation platform shown in FIG. 3, the variable b is regarded as one that is not to be loaded onto the evaluated bus because of result of the performance evaluation of the bus. That is, the restructured simulation platform has only two variables a, b that are being loaded onto the evaluated bus. Since the variable b is not loaded onto the bus, the evaluation function BUS0( ) is not embedded subsequent to the variable b to which data is written. In contrast, the evaluation function BUS0( ) is certainly embedded subsequent to the variables a, c to which data are written respectively. Thus, the evaluation function BUS0( ) is certainly executed just after the variables a, c to which the data are written respectively.

[0039] After restructuring of the simulation platform, verification is performed by simulation. Then, the bus traffic for the processing rate is calculated again in accordance with the equation (1), so that evaluation is to be performed on the performance of the bus.

[0040] Through the aforementioned operations, an average bus traffic is produced with respect to the data rate of the evaluated bus. Then, performance evaluation is performed on the bus, so that the result of the performance evaluation is fed back to structuring of the simulation platform. Hence, it is possible to actualize the architecture design at the high-level stage of design.

[0041]FIG. 4 shows a flow of steps that are performed by a computer system realizing the aforementioned bus performance evaluation method shown in FIG. 1.

[0042] With reference to FIG. 4, the flow firstly proceeds to step C1 in which a specific evaluation function is created. It is satisfactory that the evaluation function meets an operation of incrementing a certain value. Herein, the algorithm design uses sources that are described by the C language or C++ language. In step C2, the system reads the sources line by line while effecting syntax analysis.

[0043] In step C3, a decision is made as to whether the read sources describe operations of writing data to the variables loaded onto the evaluated bus or not. If so, the flow proceeds to step C4 in which the evaluation function is embedded subsequent to the variables to which the data are written respectively. Due to the aforementioned works, the evaluation function is certainly executed when the data are written to the variables loaded onto the evaluated bus, in other words, when data transfer is caused on the evaluated bus.

[0044] In step C5, a decision is made as to whether description of the sources reading in the aforementioned works is completed up to the last line of the sources originally used in the algorithm design or not. Thus, modification is effected on the sources originally used in the algorithm design. After the modification proceeds to the last line of the sources used in the algorithm design, the flow proceeds to step C6 in which the system compiles the modified sources to structure the simulation platform for use in the architecture design. In step C7, bus traffic is calculated for the evaluated bus by execution of the simulation platform. Because the processing rate requested by the main function is already known, the bus traffic for the processing rate is produced so that performance evaluation is performed on the evaluated bus in step C8.

[0045] FIGS. 5 to 10 show examples of list forms representing the bus performance evaluation methods in accordance with other embodiments of the invention. Next, those embodiments will be described in detail in comparison with the aforementioned first embodiment shown in FIG. 2.

[0046]FIG. 5 shows the bus performance evaluation method of the second embodiment that has tree variables a, b and c, which are loaded on the evaluated bus and all of which are locally defined. In addition, there are provided an evaluation function BUS0( ) and a local variable bus0( ). The evaluation function increments a static variable i to provide a return value. The local variable bus0( ) stores the return value from the evaluation function BUS0( ). That is, it represents a number of times in effecting data transfer on the evaluated bus.

[0047] All of the variables a, b and c consist of the same number of bits, which is smaller than a number of lines (or bits) of the evaluated bus. A main difference between the first embodiment of FIG. 2 and the second embodiment of FIG. 5 lies in manners of definition of the variables, that is, the variables loaded onto the evaluated bus are not defined globally but defined locally in FIG. 5. To perform performance evaluation on the bus, bus traffic for its processing rate is calculated in accordance with the aforementioned equation (1).

[0048] As the second embodiment is designed such that the variables loaded onto the evaluated bus are not defined globally but are defined locally, it proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to structuring of the simulation platform. Therefore, as similar to the first embodiment, the second embodiment allows the architecture design to be effected at the high-level stage of design.

[0049]FIG. 6 shows the bus performance evaluation method of the third embodiment that has three variables a, b and c, which are loaded onto the evaluated bus and all of which are defined globally. In addition, there are provided an evaluation function BUS0( ) and a local variable bus0( ). Herein, the evaluation function increments a static variable i to provide a return value. The local variable bus0( ) stores the return value from the evaluation function BUS0( ). That is, it represents a number of times in effecting data transfer on the evaluated bus.

[0050] All of the variables a, b and c consist of the same number of bits, which is smaller than a number of lines (or bits) of the evaluated bus. A main difference between the first embodiment of FIG. 2 and the third embodiment of FIG. 6 lies in manners of embedding of the evaluation function BUS0( ), that is, the evaluation function is embedded just before the variables to which data are written respectively. Thus, the evaluation function is certainly performed when the data are written to the variables respectively, in other words, when data transfer is effected on the evaluated bus. Incidentally, the third embodiment performs the performance evaluation upon calculation of the bus traffic for the processing rate by the aforementioned equation (1).

[0051] As described above, the third embodiment is designed such that the evaluation function BUS0( ) is embedded just before the variables to which data are written respectively, in other words, it is designed such that the evaluation function BUS0( ) is to be certainly performed when data are written to the variables respectively or when data transfer is effected on the evaluated bus. Herein, the third embodiment proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to structuring of the simulation platform. Therefore, as similar to the first embodiment, the third embodiment allows the architecture design to be effected at the high-level stage of design.

[0052] Next, a description will be given with respect to the case where all of the variables a, b and c have the same number of bits, which is greater than the number of lines (or bits) of the evaluated bus. The description will be given with respect to the case where each of the variables a, b and c consists of n bits while the evaluated bus consists of m bits (where n≧m). For example, n is set to ‘32’, and ‘m’is set to ‘8’.

[0053] In the aforementioned case, when data are written to the variables loaded onto the evaluated bus, data transfer is effected on the bus multiple times, a number of which is calculated by ‘n/m’, that is, four times. To perform the performance evaluation on the bus, bus traffic for its processing rate is calculated by the following equation (2).

(Bus traffic for the processing rate)=(number of times in execution)×4/(processing rate)  (2)

[0054] Next, further embodiments of the invention will be described with reference to FIGS. 7 to 10.

[0055]FIG. 7 shows the bus performance evaluation method of the fourth embodiment that has two variables a, b loaded onto the evaluated bus, wherein both of the variables are defined globally. In addition, there are provided an evaluation function BUS1( ) and a local variable bus1. Herein, the evaluation function BUS1( ) has two arguments, namely ‘bit’ and ‘bus’. That is, it increments a static variable i by ‘bit/bus’ to provide a return value. The local variable bus1 stores the return value from the evaluation function BUS1( ). That is, it represents a number of times in effecting data transfer on the evaluated bus.

[0056] Suppose that the variable a loaded onto the evaluated bus consists of thirty-two bits while the variable b loaded onto the evaluated bus consists of sixteen bits, wherein the evaluated bus consists of eight bits.

[0057] Different from the foregoing first embodiment of FIG. 2, the fourth embodiment of FIG. 7 deals with two bits loaded onto the evaluated bus, wherein the two variables are configured by different numbers of bits, both of which are greater than the number of bits of the evaluated bus. In addition, the fourth embodiment of FIG. 7 is characterized by that the evaluation function having two arguments ‘bit’ and ‘bus’, and it increments the static variable i to provide a return value. To perform performance evaluation on the bus, bus traffic for its processing rate is calculated by the aforementioned equation (1).

[0058] Although the fourth embodiment is designed such that the variables loaded onto the evaluated bus are configured by different numbers of bits, which are greater than the number of bits of the evaluated bus, it proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to structuring of the simulation platform. Therefore, as similar to the first embodiment, the fourth embodiment allows the architecture design to be effected at the high-level stage of design.

[0059]FIG. 8 shows the bus performance evaluation method of the fifth embodiment that has two variables a, b loaded onto the evaluated bus, which are defined by specific arrays respectively. In addition, there are provided an evaluation function BUS0( ) and a local variable bus2. Herein, the evaluation function has an argument ‘ele’, so it increments a static variable i by ‘ele’ to provide a return value. The local variable bus2 stores the return value from the evaluation function BUS2( ), so it represents a number of times in effecting data transfer on the evaluated bus.

[0060] Both of the variables a, b loaded onto the evaluated bus consist of the same number of bits, which is smaller than a number of bits of the evaluated bus. Different from the first embodiment of FIG. 2, the fifth embodiment of FIG. 8 is designed such that both of the variables loaded onto the evaluated bus are defined by specific arrays, and address transfer is effected in the main function. In addition, the fifth embodiment is characterized by that the evaluation function having an argument ‘ele’ increments the static variable i by ‘ele’ to provide a return value.

[0061] To perform performance evaluation on the bus, bus traffic for its processing rate is calculated by the aforementioned equation (1).

[0062] Although the fifth embodiment is designed such that the variables loaded onto the evaluated bus are defined by the specific arrays, and the address transfer is effected in the main function, the fifth embodiment proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to structuring of the simulation platform. Therefore, as similar to the first embodiment, the fifth embodiment allows the architecture design to be effected at the high-level stage of design.

[0063]FIG. 9 shows the bus performance evaluation method of the sixth embodiment that has two variables a, b loaded onto the evaluated bus, wherein the variables are both defined globally. In addition, there are provided an evaluation function BUS3( ) and a global variable ‘bus’. The evaluation function increments the global variable ‘bus’. The global variable ‘bus’ represents a number of times in effecting data transfer on the evaluated bus.

[0064] Both of the variables a, b consist of the same number of bits, which is smaller than a number of bits of the evaluated bus. Different from the first embodiment of FIG. 1, the sixth embodiment of FIG. 9 is characterized by that the variables to be incremented by the evaluation function are defined globally.

[0065] To perform performance evaluation on the bus, bus traffic for its processing rate is calculated by the foregoing equation (1).

[0066] Although the sixth embodiment is designed such that the variables to be incremented by the evaluation function are defined globally, the sixth embodiment proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to structuring of the simulation platform. Therefore, as similar to the first embodiment, the sixth embodiment allows the architecture design to be effected at the high-level stage of design.

[0067]FIG. 10 shows an example of a simulation platform that is structured by sources described by the C++ language.

[0068] In the simulation platform shown in FIG. 10, there are provided three buses, namely ‘bus0’, ‘bus1’ and ‘bus2’ which are subjected to BUS class definition as well as three variables a, b and c. Herein, the variable a is defined globally and is loaded onto the bus bus0. The variable b is defined locally and is loaded onto the bus bus1. The variable c is defined by a specific array and is loaded onto the bus bus2.

[0069] There is provided a BUS class, which has a function ‘count( )’ for incrementing a member variable i by ‘1’ as well as two arguments, namely ‘bit’ and ‘bus’. In addition, there are provided a function ‘Count_bit( )’ for incrementing the member variable i by ‘bit/bus’ and an argument ‘ele’. Further, a function ‘count_hairetu( )’ for incrementing the member variable i by ‘ele’ is defined. Therefore, the member variable i within the BUS class represents a number of times in effecting data transfer on the evaluated bus.

[0070] Both of the variables a, c loaded onto the evaluated bus consists of the same number of bits, which is smaller than numbers of bits of the buses bus0 and bus1 respectively. In addition, the variable b loaded onto the evaluated bus consists of thirty-two bits, while the bus bus1 consists of eight bits.

[0071] Different from the foregoing embodiments (including the first embodiment of FIG. 2), the simulation platform of FIG. 10 is characterized by the sources being described by the C++ language. To perform performance evaluation on the bus, bus traffic for its processing rate is calculated by the aforementioned equation (1).

[0072] Although the simulation platform is structured using the sources described by the C++ language as shown in FIG. 10, it proceeds to calculation of the bus traffic for the processing rate and performance evaluation of the bus, then, it feeds back the result of the performance evaluation to restructuring of the simulation platform. Therefore, it is possible to carry out the architecture design at the high-level stage of design.

[0073] As described heretofore, this invention is designed such that when data transfer is caused on the bus interconnecting between the hardware and software to be evaluated, the sources that are used in the architecture design and are described by the general purpose high-level language such as the C language and C++ language are modified by executing the specific evaluation function, so that the simulation platform for use in the architecture design is structured. Then, simulation is performed using the structured simulation platform to calculate the bus traffic for the processing rate of the evaluated bus. Thus, it is possible to perform the bus performance evaluation at the high-level stage of design.

[0074] Result of the bus performance evaluation is fed back to the sources that are used in verification of the algorithm(s). This enables the architecture design to be performed at the high-level stage of design. So, it is possible to reduce overall simulation time that is necessary for the architecture design. In addition, this invention is characterized by placing the cooperative verification on the unification of the hardware and software as one type of simulation that merely performs operational confirmation. That is, it is possible to exclude actual designing steps from the cooperative verification, so it is possible to considerably reduce the time and cost that are needed for design and development of the logic circuits, systems and devices.

[0075] As described heretofore, this invention has a variety of effects and technical features, which will be described below.

[0076] (1) When data are written to variables loaded onto the evaluated bus, sources that are described by the general purpose high-level language such as the C language and C++ language for use in the algorithm design are modified by executing a specific evaluation function for increment by a certain value, so that a simulation platform is structured. Hence, bus traffic is calculated in connection with the processing rate of the bus interconnecting between the hardware and software, so bus performance evaluation can be performed at the high-level stage of design in the LSI design and development. In addition, result of performance evaluation of the bus is fed back to structuring of the simulation platform, so it is possible to perform the architecture design at the high-level stage of design. Because the architecture design is performed using the sources that are described by the general purpose high-level language for use in the algorithm design, it is possible to considerably reduce overall simulation time for the architecture design. Generally speaking, as compared with the HDL, the C language and C++ language are increased in simulation speed to be approximately one-thousand times higher.

[0077] (2) Because the architecture design is performed using the sources that are described by the general purpose high-level language, it is possible to simplify feedback procedures due to the architecture design. By optimally performing isolation of the hardware and software at the prescribed stage of the architecture design, it is possible to exclude feedback loops regarding the isolation of the hardware and software from the cooperative verification after the actual coding. This guarantees considerable reduction of the turnaround time of design. As compared with the HDL and other assembly languages, the C language and C++ language can be described using a relatively small number of codes. That is, those languages can be easily changed and modified according to needs.

[0078] (3) This invention places the cooperative verification on unification of the hardware and software as one type of simulation for merely performing operational confirmation, wherein no design is newly performed. This brings exclusion of the feedback loops being derived from the cooperative verification. That is, it is possible to reduce a number of times in effecting simulation in RTL, so it is possible to considerably reduce overall time and cost for the design of circuitry. Such an effect becomes substantial as the scale of circuitry being manufactured increases.

[0079] As this invention may be embodied in several forms without departing from the spirit of essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds are therefore intended to be embraced by the claims. 

What is claimed is:
 1. A bus performance evaluation method for algorithm description in which evaluation is performed on performance of a bus interconnecting between hardware and software by using sources described by a general purpose high-level language for verification of an algorithm, said bus performance evaluation method comprising the steps of: modifying the sources by executing a specific evaluation function when data transfer is caused on the bus; and in response to modified sources, structuring a simulation platform for use in an architecture design.
 2. A bus performance evaluation method for the algorithm description according to claim 1 further comprising the step of performing simulation using the simulation platform to allow calculation of bus traffic for a processing rate of the bus, so that the evaluation of the performance of the bus is performed at a high-level stage of design.
 3. A bus performance evaluation method for the algorithm description according to claim 1 or 2 further comprising the step of: feeding back result of the evaluation of the performance of the bus to the sources used in the verification of the algorithm, so that the architecture design is performed at a high-level stage of design.
 4. A bus performance evaluation method for algorithm description in which evaluation is performed on performance of a bus interconnecting between hardware and software by using sources described by a general purpose high-level language for verification of an algorithm, said bus performance evaluation method comprising the steps of: structuring a simulation platform for use in an architecture design by using the sources; performing the evaluation of the performance of the bus by using the simulation platform; modifying the sources in response to result of the evaluation of the performance of the bus; restructuring the simulation platform in response to the modified sources; and performing the evaluation again on the performance of the bus by using the restructured simulation platform.
 5. A bus performance evaluation method for the algorithm description according to claim 4 wherein structuring the simulation platform for use in an architecture design using the sources comprises the steps of analyzing the sources by prescribed units respectively to isolate a hardware portion and a software portion; creating an evaluation function for counting bus traffic of the bus; and effecting syntax correction on the sources by executing the evaluation function every time data transfer is caused on the bus.
 6. A bus performance evaluation method for the algorithm description according to claim 4 wherein the evaluation is performed on the performance of the bus by using the evaluation function, so that in response to the bus traffic that is finally produced with respect to the processing rate of the bus, isolation of the hardware and software is optimized.
 7. A bus performance evaluation method for algorithm description in which evaluation is performed on performance of a bus interconnecting between hardware and software by using sources described by a general purpose high-level language, said bus performance evaluation method comprising the steps of: creating an evaluation function for counting bus traffic of the bus; sequentially reading in the sources line by line while effecting syntax analysis; making a determination as to whether description of the sources represent writing data to variables that are defined in advance and are loaded onto the bus to be evaluated; upon the determination, modifying the sources by using the evaluation function that is embedded just before or just after the variable to which the data is written; repeating the foregoing steps until the sources are completely read in and modified up to a last line; structuring a simulation platform for use in an architecture design by compiling the sources being modified; performing calculation on the bus traffic for the bus by executing the simulation platform; producing the bus traffic with regard to a processing rate of the bus that is already known; and performing the evaluation on the performance of the bus in response to the bus traffic being produced.
 8. A bus performance evaluation method for the algorithm description according to claim 7 wherein the variables loaded onto the bus consist of n bits while the bus consists of m bits (where n, m are both integral numbers, and n≦m), so that the bus traffic for the processing rate is produced such that a number of times in effecting data transfer on the bus is multiplied by n/m and is then divided by the processing rate.
 9. A bus performance evaluation method according to any one of claims 1, 4 and 7 wherein the general purpose high-level language is C language or C++ language.
 10. A bus performance evaluation method according to any one of claims 1, 5 and 7 wherein the evaluation function is to increment a pre-defined variable loaded onto the bus. 